Robust negative bit-line and reliability aware write assist

ABSTRACT

A reliability aware negative bit-line write assist (RA-NBL) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at a high voltage.

RELATED APPLICATIONS

The present application claims priority to U.S. Provisional PatentApplication No. 62/348,138 filed Jun. 9, 2017, and incorporates thatapplication in its entirety.

FIELD OF THE INVENTION

The present invention is related to write assist, and in particularwrite assists in ultra-low power applications.

BACKGROUND

Memory devices are used as storage for digital data in a lot ofelectronic integrated circuits (ICs), for example in computers,processors, microcontrollers etc. One basic type of a memory device isRandom Access Memory (RAM) which is of two types: static RAM (SRAM) anddynamic RAM (DRAM). In a SRAM memory an array of cells is used to storedata and each cell can store one bit of data i.e. “0” or “1”. A typicalSRAM consists of a pair of cross-coupled inverters which form a latch tostore the data. Data to be written into this cell is driven from the bitlines which are connected to these cross-coupled inverters via passgates which are typically N-type Metal Oxide Semiconductor Field EffectTransistor (MOSFET) devices (NMOS).

For a successful write operation, the data on the bitlines should bestrong enough to overpower the cross-coupled inverter latch to write thenew data on the cell. In part because of their uses in biomedical andInternet-of-Things (IOT) applications, the supply voltage of suchdevices has been scaled down. As a direct result of this scaling down ofthe supply voltage, the writeability of the SRAM cell has deteriorated.As the technology is shrinking there are significant concerns aboutpower dissipation and leakage of memory devices as well.

Various methods of implement write assist (WA) circuits have beenproposed to improve the write performance of SRAM cells. The most widelyused method is the negative bitline write assist technique. In thistechnique, the bitline through which “0” is being written is drivenbelow the reference ground voltage to strengthen the pass gates byincreasing its source-gate voltage.

In the prior art technique, a negative voltage bump is generated on thebitline by using coupling capacitor. The bump is directly proportionalto the size of capacitor and supply voltage. To achieve successful lowvoltage write operation a large capacitor is required. However, using alarge capacitor means a larger negative bump at higher supply voltages,when no negative bump is needed. Having the larger negative bump acauses severe reliability and aging issue to the SRAM cell. Thisoverstressing may lead to oxide breakdown of the NMOS pass gate andcause a loss of yield of SRAM cell. The reliability concern has a hugeimpact on fabrication costs as well as the lifespan of the memory deviceand consequently the whole electronic system on chip (SoC). Also, alarge negative bump can create data retention issues in unselected SRAMcells where pass gates can be turned on due to increased gale-sourcevoltage. These issues are especially apparent when the SRAM celloperates in ultra-low voltage applications (IoT, wireless and biomedicalapplication).

BRIEF DESCRIPTION OF THE FIGURES

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 is a block level representation of one embodiment of aReliability Aware-Negative Bit-line Write Assist scheme (RA-NBL)circuit.

FIG. 2 is a circuit level representation of one embodiment of aReliability Aware-Negative Bit-line Write Assist scheme (RA-NBL)circuit.

FIG. 3A is an exemplary waveform at low voltage and low temperature,using the RA-NBL circuit.

FIG. 3B is an exemplary waveform at high voltage and high temperatureusing the RA-NBL circuit.

FIG. 4A is a table of bitcell characteristics at various temperaturesand voltage levels.

FIG. 4B is a table of exemplary negative bump values generated by theRA0NBL circuit.

FIG. 5A illustrates embodiments of the charging level across the worstprocess corner with varying supply voltages at −40 C and 125 C and itsstatistical variation respectively.

FIG. 5B illustrates embodiments of charging level across temperatures atthe worst process corner of a write operation.

FIG. 6 is a block diagram of one embodiment of an SRAM circuit includingthe RA-NBL circuit.

DETAILED DESCRIPTION

A memory device can be operated in a wide range of voltages. To writedata in SRAM memory, the write assist circuit is useful in the lowvoltage and low temperature domain but there is no need of any assistcircuit when operating in high voltage and high temperature domain.Furthermore, having a write assist when not needed can lead todegradation of the memory. To provide a selective write assist, thewrite assist circuit needs to be switched on and off based on theoperating voltage externally. This is especially useful in System onchip (SoC) environments.

The present system is a Reliability Aware-Negative Bit-line Write Assist(RA-NBL) circuit. The RA-NBL circuit, in one embodiment, permits thewrite assist circuit to operate seamlessly from low to high voltagewithout the need to manage an additional pin for controlling thenegative bump. This control is provided by generating a tuned negativebias that is close to the expected write assist requirement for SRAMacross a wide operating voltage range. By enabling a large negative bumpat lower supply voltage, without overstressing the device at highersupply voltage, the system enables a wide range of voltages to be used.This allows memory to meet the specification of ultra-low voltageapplications which is very important in terms of the market requirementtoday for IoT, biomedical technologies and wireless sensor applications.

The problem of reliability and aging is also highly sensitive totemperature. The RA-NBL circuit, in one embodiment, aims to resolve thisby reducing negative bump at higher temperatures to relax the SRAMstress condition. This improves the ageing and yield of the SRAM. In oneembodiment, the RA-NBL circuit also controls the negative bump value atmid- to high operating voltages improving the overall performancecompared to having no write assist circuit.

The system has different negative voltage bumps at high and lowtemperatures. While the discussion references “high” temperature and“low” temperature, the actual adjustment is continuous between varioustemperatures. In one embodiment, high temperature is in the range of 125C, while low temperature is −40 C. In one embodiment, operatingtemperatures above room temperature are considered high temperature,while operating temperatures below room temperature are considered lowtemperature. In another embodiment, there is a third temperature rangeof “normal temperature,” where the temperature ranges are high (80 C to125 C), normal (80 C to 0 C) and low (0 C to −40 C). Other divisions oftemperature may be used. In one embodiment, the voltage range may befrom 1V to 0.5V.

FIG. 4A shows a table illustrating bitcell characteristics, showing thenegative bump needed for a successful write operation for the worstprocess corner (slow NMOS, fast PMOS). The table illustrates exemplarynegative bumps needed for a high density bitcell 7 nm technology. As canbe seen, at a high voltage, and high temperature (125 C), no bump isused above 0.7V, and a −25% bump is used at 0.5V. At a low temperature(40 C) the negative bump at 0.5V is −40°% while at 0.75V it's −8% only.Above 0.75V, no bump is needed at either temperature. The RA-NBL circuitis designed, in one embodiment, to provide a larger negative voltagebump than the bitcell characteristics illustrated in FIG. 3A. The RA-NBLcircuit, in one embodiment, also resolves the data retention issue facedby unselected cells by maintaining a low gate-source voltage on the passgates across the entire operative voltage range of memory.

The RA-NBL circuit is designed to improve the writeability of a SRAMbitcell by adding a negative bias to the bitline for low voltage,without stressing the devices at high voltage. In one embodiment, thecircuit consists of a coupling capacitor for generating the negativebias. In one embodiment, the control block consists of a circuit whichcharges the coupling capacitor to a certain voltage and then dischargesit during the write operation. In one embodiment, the block consists ofa NMOS transistor connected in a gate-drain terminal connectedconfiguration to control the charging of the capacitor. The gate-drainconnected NMOS, or diode-connected device, acts as a voltage limiter,which is voltage and temperature dependent.

One of the skill in the art is well aware of the several write assisttechniques circuits are available in the literature, including VDDlowering of SRAM cell, VSS raising of SRAM cell, Word-line boosting andNegative Bit-line write assist technique. The negative bit-line schemehas been a widely used solution. The negative bit-line scheme creates anegative bump for write assist, which helps to achieve a negative biasvoltage on the SRAM's bit-lines. Therefore, in this context a “higher”negative bump is a larger amplitude, e.g. a lower voltage.

The following detailed description of embodiments of the invention makesreference to the accompanying drawings in which like references indicatesimilar elements, showing by way of illustration specific embodiments ofpracticing the invention. Description of these embodiments is insufficient detail to enable those skilled in the art to practice theinvention. One skilled in the art understands that other embodiments maybe utilized and that logical, mechanical, electrical, functional andother changes may be made without departing from the scope of thepresent invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims.

FIG. 1 is a block diagram of one embodiment of the RA-NBL circuit. Inone embodiment, the RA-NBL circuit 100, is coupled between a writedriver 110, and a switch 120 to ground 125. The write driver 110controls writing in the SRAM cell 130. The RA-NBL circuit 100 in oneembodiment has the following components: a voltage limiting circuit 150,a charging circuit 160, a coupling capacitor 170, a discharging circuit180, and a control input generator 190.

The charging circuit 160 charges coupling capacitor 170, which providesthe negative bump. Charging circuit 160 is controlled by voltagelimiting circuit 150. In one embodiment, the voltage limiting circuit150 controls the gate drive of charging circuit 160, and acts as voltagelimiting device. The coupling capacitor 170 is charged by chargingcircuit 160, and is pulled down to VSS (ground) through dischargingcircuit 180. The sequence of charging the coupling capacitor 170 and itsdischarging is controlled by control input generator 190. Control inputgenerator 190 also controls switch 120, which in turn provides input towrite driver 110.

The RA-NBL circuit generates a negative voltage through a couplingcapacitor 170 in a tunable manner so that the maximum negative voltageis generated at low voltage and temperatures.

In one embodiment, RA-NBL circuit 100 including coupling capacitor 170may be shared across multiple columns of an SRAM array.

FIG. 6 illustrates one embodiment of an SRAM system including the RA-NBLcircuit. SRAM system 600 includes a plurality of SRAM cells 610A-610N,and an RA-NBL circuit 620. As can be seen, in one embodiment, an RA-NBLcircuit 620 is shared between a plurality of SRAM cells 610A-610N. SRAMcells 610A-610N are in proximity, and thus are likely to experience thesame voltage and temperature levels. In one embodiment between 32 and1024 SRAM cells may be coupled to an RA-NBL circuit 620. In oneembodiment, a typical configuration may include 512 SRAM cells coupledto the RA-NBL circuit 620. In one embodiment, the coupling capacitorsize depends on the bitline capacitance per SRAM cell and the number ofSRAM cells across which the RA-NBL circuit is shared multiplied by aconstant, which depends on the technology parameters and negativevoltage requirement.

FIG. 2 is a circuit diagram of one embodiment of the RA-NBL circuit 100.Here is an example of single port SRAM cell 210 is shown as oneembodiment of the circuit. However, one of skill in art can understandthat similar memory devices and operations can implement multi-portmemory cells. The SRAM cell 210 can store one bit of logical data. Writeline 215 can be enabled to connect SRAM cell 210 to the bit lines 220and 225 through which data to be written in the memory cell is driven.While only one memory cell is shown in the memory device, one of skillin the art would understand that memory devices have many memory cellsarranged in various configurations, and that a single RA-NBL circuit candrive a plurality of memory cells, in one embodiment. In one embodiment,the memory system also consists of write driver circuit 230 which iscoupled to the memory cell through the bit lines 220 and 225.

Data to be written is controlled by signal 233 and 235, enabling theNMOS in write driver circuit 230. The memory system in one embodimentincludes coupling capacitance circuit 240 to provide the negativevoltage to either of bit line 220 and 225 via the write driver circuit230.

In the static condition, both nodes 242 and 244 of capacitor 240 are atGND. Write assist operation has two phases. The high rising signal 245starts the first phase of write assist operation. During the firstphase, the node 242 of coupling capacitor 240 is charged to providenegative voltage. The second phase of write Assist operation isinitiated by rising edge of signal 250. When signal 250 rises, it turnsOFF charging of coupling capacitor 240 by turning OFF PMOS 289. In oneembodiment, this occurs after a delay. In one embodiment, the delay iscaused by programmable inverters 260 and 262. Delayed version of signal250 turns off write driver circuit 230 (NMOS) that provides GND path toeither of bit-line 220 and 225. Once writer driver circuit 230 turnsOFF, the coupling capacitance of capacitor 240 discharges to GND throughNMOS devices 264 and 266. Thus, negative voltage is generated throughthe coupling capacitor 240 and this negative voltage is transfer toeither bit-line 220 and 225 depending ON and OFF state of NMOS 264 and266.

To align negative voltage generation with reliability, optimally thecoupling capacitor 240 is fully charged at low voltage, but chargedminimally or not at all at high voltage, This is achieved, in oneembodiment, by voltage limiting circuitry 280. In one embodiment,voltage limiting circuitry 280 includes circuitry which limits thecharging voltage for the capacitor 240 based on the voltage level (Vdd)and based on the temperature level. Voltage limiting component 280 cutsoff the charging path of the coupling capacitor 240 at high voltageand/or temperature, to ensure a minimum negative voltage is generated.High voltage and high temperature is also referred to as “stresscondition,” because it causes stress on the SRAM memory.

In one embodiment, the voltage limiting circuit 280 includes agate-drain connected PMOS transistor 282 with gate-drain connected NMOStransistor 283. The difference between the supply voltage and thresholdvoltage of the PMOS transistor 282 and NMOS transistor 283 determinesthe amount of the current flowing though PMOS 284. This difference islarger at higher voltages and/or higher temperatures.

FIG. 4B illustrates a table of one embodiment of the negative voltagebump that may be provided by the RA-NBL circuit. In one embodiment, thevoltage limiting circuit 280 provides a negative bump that is largerthan the negative bump needed by even the worst process corner at thedesignated voltage and temperature levels, as shown in FIG. 4A.

In an alternate embodiment, a PMOS transistor 282 may be used. Using acombination of the PMOS transistor 282 and the NMOS transistor 283reduces the impact of process variation. The combined PMOS 282 and NMOS283 provide process compensation across all corners. However, the PMOStransistor 282 without NMOS transistor 283 is also functional, and maybe used in one embodiment.

The gate of the PMOS 287 of the charging circuit 270 charges node 242through PMOS 287, PMOS 288, and PMOS 289. In one embodiment, PMOS 287,288, 289 are coupled in series to a finite pulse width controlled bycontrol input generator 290. In one embodiment, the finite pulse iscontrolled by a programmable inverter chain 292 and 294. The gate driveof PMOS 287 will depend on the signal at node 293 from voltage limitingcircuit 280. The gates of PMOS 288 and PMOS 289 are controlled by node269 and 268 respectively, which are outputs from the programmableinverter chain 292 and 294.

In one embodiment, node 293 is initialized to low supply rail at thebeginning of the write cycle for the memory device. The voltage level atnode 293 depends on the voltage limiting circuit 280 that is voltage andtemperature dependent. Gate signal at node 293 of PMOS 287 of thecharging circuit 270 remains at VSS during the charging period ofcoupling capacitor 240 at low voltage as shown in FIG. 3A, while at highvoltage gate signal at node 293 of PMOS 287 charges quickly to highervalue that charges coupling capacitor 240 through weakly on PMOS 287during charging time as shown FIG. 3B.

As shown in FIG. 3A, node 242 of coupling capacitor 240 is charged tofull level that generates high negative voltage at low voltage and lowtemperature. In one embodiment, the high negative voltage is ˜−80 mV.This high negative voltage bump charges the coupling capacitor 240. Thisnegative voltage bump at node 244 transfers to bit lines 220, 225through NMOSs 233, 235. In one embodiment, the maximum negative voltageis 60 mV to 100 mV. In one embodiment, the high negative voltage isapproximately 80 mV.

With respect to waveform as shown in FIG. 3B for high voltage and hightemperature, node 242 of coupling capacitor 240 is in one embodimentcharged to 20% level of supply voltage that generates negative voltageat node 244 that is transferred to bit line. In one embodiment, thecoupling capacitor 240 is charged to between 12 mV and 30 mV. In oneembodiment, ˜−20 mV negative voltage is generated at node 244 of thecoupling capacitor 240.

FIG. 5A illustrates exemplary charging levels for coupling capacitor, atvarious VDD. As shown, in one embodiment, the capacitor is more that 95%of VDD at lower voltage and low temperature at less than 25% of VDD athigh temperature and voltage. This lower charging level translates tomuch lower negative bias generation at higher temperature. This reducesor eliminates the issues of reliability and ageing at high voltage.

FIG. 5B illustrates an exemplary relationship between the temperatureand charging level. FIG. 5B illustrates the worst write corner, in oneexemplary implementation. At high voltage, there is relatively littletemperature dependency in the charging level. Reliability due tooverdrive is a major concern at high temperatures, and there is a muchlower need for the negative bump for the write assist operation. In oneembodiment, as noted above, the temperature sensitivity of gate-draincoupled PMOS device (shown as PMOS device 282 in FIG. 2) and NMOS device(shown as NMOS device 283 in FIG. 2) are used to set this ratio. Theexemplary relationship shown here is for the worst write corner.

Thus, the present application discloses a voltage and temperaturedependent write assist using a negative bump which may be used toincrease the reliability of SRAM. The system reduces the negative bumpat higher voltages, and reduces the negative bump at highertemperatures. In one embodiment, by applying a large negative bump atlow voltage, without any concern of reliability at higher voltage, theprocess enables the system to perform a fast write operation. Becausethere is no concern about the impact of the negative bump at high power,the system may be used to effectively boost power, speed, andperformance in low voltage operating zone. It can also improve writeperformance of memory systems in nominal voltage by providing an assistto write operation.

This technique is useful to provide a write assist in SRAM. However, oneof skill in the art would understand that this methodology may be usedin any to solve over-drive reliability problems in other systems, whereover-drive voltage is generated with the coupling capacitor.

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention asset forth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

We claim:
 1. A reliability aware negative bit-line write assist (RA-NBL)circuit for an SRAM (static random access memory) comprising: a couplingcapacitor to provide a negative voltage bump for write assist; a controlinput generator to charge the coupling capacitor, such that the negativevoltage bump is at a first level when the SRAM is operating at a firstvoltage, and the negative bump is at a second level lower than the firstlevel when the SRAM is operating at a second higher voltage.
 2. TheRA-NBL circuit of claim 1, wherein at the first voltage the couplingcapacitor is fully charged, and at the high voltage the couplingcapacitor is partially charged.
 3. The RA-NBL circuit of claim 1,wherein at a low temperature the coupling capacitor is fully charged,and at a high temperature the coupling capacitor is partially charged.4. The RA-NBL circuit of claim 1, further comprising: a voltage limitingcircuit to charge the coupling capacitor.
 5. The RA-NBL circuit of claim4, wherein the voltage limiting circuit comprises a gate-drain connectedPMOS circuit and a gate-drain connected NMOS circuit.
 6. The RA-NBLcircuit of claim 4, further comprising: a charging circuit to charge thecoupling capacitor, the charging circuit controlled by the voltagelimiting circuit.
 7. The RA-NBL circuit of claim 6, further comprising:a discharging circuit to pull down a charge of the coupling capacitor toVss.
 8. A method of utilizing a reliability aware negative bit-linewrite assist (RA-NBL) circuit, the method comprising: pre-charging acoupling capacitor to a level determined based on Vdd; when writing amemory cell, utilizing the coupling capacitor to provide a negativevoltage bump, the negative voltage bump at a first level when the Vdd isat a first value, and the negative voltage bump is at a second, lower,level when the Vdd is at a second value higher than the first value. 9.The method of claim 8, wherein when the Vdd is low the couplingcapacitor is fully charged, and when the Vdd is high the couplingcapacitor is partially charged.
 10. The method of claim 8, wherein at afirst temperature the coupling capacitor is fully charged, and at asecond temperature, higher than the first temperature, the couplingcapacitor is partially charged.
 11. The method of claim 8, furthercomprising: charging the coupling capacitor in a voltage and temperaturedependent manner through a voltage limiting circuit comprising agate-drain connected PMOS circuit and a gate-drain connected NMOScircuit.
 12. The method of claim 8, further comprising: pulling down acharge of the coupling capacitor to Vss, though a discharging circuit.13. A system comprising: an SRAM cell; a write driver coupled to theSRAM cell; a coupling capacitor coupled to the write driver, thecoupling capacitor to provide a negative voltage bump of a first levelwhen a Vdd is low; and a charging circuit to charge the couplingcapacitor to a first level when the Vdd is at a first value, and to asecond level below the first level when the Vdd is at a second valuehigher than the first value.
 14. The system of claim 13, wherein thefirst level is fully charging the coupling capacitor, and at the secondlevel is partially charged.
 15. The system of claim 13, furthercomprising: the charging circuit to charge the coupling capacitor to ahigher level when a temperature is lower than when the temperature ishigher.
 16. The system of claim 13, further comprising: a voltagelimiting circuit to charge the coupling capacitor, the voltage limitingcircuit comprising a gate-drain connected PMOS circuit and a gate-drainconnected NMOS circuit.
 17. The system of claim 16, further comprising:a charging circuit to charge the coupling capacitor, the chargingcircuit controlled by the voltage limiting circuit.
 18. The system ofclaim 13, further comprising: a discharging circuit to pull down acharge of the coupling capacitor to Vss.
 19. The system of claim 13,comprising: a voltage limiting circuit comprising a gate-drain coupledMOS element, the gate-drain coupled MOS element being sensitive totemperature and voltage level, to limit the charging voltage of thecapacitor based on the temperature level.
 20. The system of claim 13,wherein the write driver is coupled to a plurality of SRAM cells, andused to provide the negative bump to the plurality of SRAM cells.